The present invention relates to an address translation system, and in particular, to an address translation system which is used in a virtual storage system requiring address translation for an access to the main storage and is capable of facilitating access particularly from the input/output devices to the main storage.
In a virtual storage system which requires address translation to access the main storage device, it has been an essential problem to determine a location where the address translation is to be effected.
In a conventional example as illustrated in FIG. 1, for example, in the VAX-11 of the Digital Equipment Corp. (to be simply referred to as the VAX method herebelow; "VAX Hardware Handbook" (1980), pp. 202, 203, 206, 207, 316, and 317), as shown in FIG. 1, a logical address outputted from a central processing unit (CPU) 1 is translated into a physical address by means of an address translator 2 for the CPU 1. When an input/output device 5 directly accesses a storage device 3 without assistance from the CPU 1, namely, in the operation of a direct memory access (DMA), the logical address outputted from the input/output device 5 is translated into a physical address by means of an input/output address translator 4. These physical addresses thus obtained are supplied via an address bus 10 to the main storage 3.
According to the VAX method, when a plurality of input/output devices are utilized, it is necessary to develop an address translator dedicated to each input/output device or to each group of input/output devices and to connect the address translator between the input/output device 5 and the memory address bus 10.
In the VAX method as described above, if the address translation into a physical address necessary to access the storage device is achieved at the output each input/output device, a dedicated address translator is required to be prepared for each input/output device, which leads to a problem concerning the cost thereof.
As an improvement of the VAX method, an address translation method can be considered in which the cost on the input/output device side is lowered by removing the input/output address translator 4 from the system configuration of FIG. 1, whereas the address translator 2 for the CPU 1 is kept.
In this method, however, in which the address translator for the input/output device is omitted, and only the address translator for the CPU utilized, the physical address in the main storage unit must be directly outputted from each input/output device. Consequently, for example, when transfer of data involving a plurality of pages is to be executed between a magnetic disk unit and the main storage device, successive storage areas in the physical space of the storage device 3 must be allocated to the magnetic disk to facilitate the address generation of the magnetic disk unit. This leads to a problem that the advantageous features of the virtual storage system cannot be efficiently utilized, which means as a result the data transfer employing the DMA is limited to a one page operation.
An example of a data processing system not having an address translator at the output of an input/output device has been described in "The Design and Implementation of the MC68851 Paged Memory Management Unit", IEEE MICRO magazine vol. 6, No. 2 (April, 1986), pp. 13-28 (see particularly FIG. 1 in page 13).
Reference may be made to the U.S. Pat. No. 4,550,368 concerning a construction of memory systems of computers involving an address translation.